Sigma-delta (Σ-Δ) modulation is a widely used and thoroughly investigated technique for converting an analog signal into a high-frequency digital sequence. See, for example, “Oversampling Delta-Sigma Data Converters,” eds. J. C. Candy and G. C. Temes, IEEE Press, 1992, (hereinafter Candy) and “Delta-Sigma Data Converters,” eds. S. R. Northworthy, R. Schreier, G. C. Temes, IEEE Press, 1997, both of which are hereby incorporated herein by reference.
In Σ-Δ modulation, a low-resolution quantizer is incorporated within a feedback loop configuration in which the sampling frequency is much higher than the Nyquist frequency of the input signal (i.e., much higher than twice the maximum input frequency). In addition, the noise energy introduced in the quantizer is shaped towards higher frequencies according to a so called “noise-transfer-function” NTF(z), and the signal passes the modulator more or less unchanged according to a so called “signal-transfer-function” STF(z).
FIG. 1(a) depicts a simple first order Σ-Δ modulator for a discrete time system having a subtraction stage 101, an accumulator 102 (including an integrator adder 103 and a delay line 104), a one-bit quantizer 105, and a 1-bit digital-to-analog converter (DAC) 106. In normal operation, an input signal x(n) within the range [−a, +a] is converted to the binary output sequence y0(n) ε±1. Quantizer 105 produces a +1 for a positive input and a −1 for a negative input. The output from quantizer 105 is fed back through DAC 106 and subtracted from input signal x(n) by subtraction stage 101. Thus, the output of subtraction stage 101 represents the difference between input signal x(n) and the quantized output signal y0(n). As can be seen from FIG. 1(a), the output of accumulator 102 represents the sum of its previous input and its previous output. Thus, depending on whether the output of the accumulator 102 is positive or negative, the one-bit quantizer 105 outputs a +1 or a −1 as appropriate. Herein, and in the appended claims, analog (physical) and digital representations of signals are distinguished from each other by labeling digital one or multi-bit signals with the subscript “0”.
In FIG. 1(b), a linear model of FIG. 1(a) is shown, and similarly includes a subtraction stage 107, and an accumulator 111 (including an integrator adder 112 and a delay line 113). Quantizer 105 is replaced by an adder 108 and a noise source 109. To convert signal y(n) to y0(n), a comparator 110 for detection of the sign of y(n) is included. The basic relationship between the z-transforms of system input x(n), quantizer noise γa(n), and the two-level output sequence y(n) is:Y(z)=z−1X(z)+(1−z−1)Γa(z)  (1)The signal transfer function and noise-transfer function can be identified as STF(z)=z−1 and NTF(z)=(1−z−1), respectively.
Quality of digital representation can be described by the signal-to-noise ratio
      SNR    -          10      ⁢                          ⁢              log        10            ⁢              S        N              ,where S is the signal power and N is the noise power within a given bandwidth B. Regarding equation (1), the noise power N depends on both the noise transfer function NTF(z) and the overall amount of noise Γa(z) added in the quantization stage. To improve the SNR, two approaches can be pursued:                (a) for a given overall noise power Γa(z), i.e., for given quantizer levels ±a, modify the NTF(z) to remove more noise power from the base band by improved noise shaping, and        (b) for a given NTF(z), try to reduce the overall noise power introduced to the system.        
Approach (a) can be achieved, for example, by increasing the order of the sigma-delta modulator, as described by Candy. For higher order modulators, the noise transfer function becomes NTF(z)=(1−z−1)k, which means an enhanced noise-shaping effect. For examples of approach (b) see Zierhofer C. M., “Adaptive sigma-delta modulation with one-bit quantization,” IEEE trans. CAS II, vol. 47, No. 5, May 2000 (hereinafter Zierhofer), and U.S. patent application for Adaptive Sigma-delta Modulation with One-bit Quantization, Ser. No. 09/496,756, filed Feb. 3, 2000, which issued as U.S. Pat. No. 6,535,153 (hereinafter U.S. patent application Ser. No.: 09/496,756), both of which are incorporated herein by reference, where a sigma-delta modulator is employed within a feedback loop configuration. It is shown that the input signal of this modulator applies within a reduced range, and thus the two levels of the quantizer can be reduced. As a consequence, less noise power is introduced to the system, and the SNR is improved.